• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An integrated circuit device having at least two elements includes insulating structures 4 ', 5 on the substrate. The structure covers at least one side of the trench 3 and is wider at the bottom of the trench than at the trench neck. The devices are arranged in different planes at the substrate surface and the trench bottom. The insulating structure ensures vertical isolation between the elements.
    公开号:KR19990014889A
    申请号:KR1019970708234
    申请日:1996-06-24
    公开日:1999-02-25
    发明作者:프랭크 라우；볼프강 크라우트슈나이더；만프레트 엥엘하르트
    申请人:로더리히네테부쉬；지멘스악티엔게젤샤프트；
    IPC主号:
    专利说明:

    Integrated circuit device having at least two elements insulated from each other and method of manufacturing the same
    Trench isolation is used in semiconductor technology, in particular MOS technology, to electrically insulate the devices within a substrate, which are given a small area of insulation. The longitudinal trench completely filled with SiO 2 is mainly used as trench isolation. The depth of the trench generally corresponds approximately to the minimum structural dimension in the individual technique.
    Leakage current in the bulk is prevented by trench isolation. If the insulating and conductive layers are arranged on the surface of the trench, leakage current will occur at the surface due to the parasitic MOS device. This leakage current must also be prevented by trench isolation.
    To improve the insulating behavior of trench isolation, doped regions are used in the trench isolation regions to prevent the formation of conductive channels. Such doped regions are generally formed by implantation. However, this implantation can affect the parameters of devices that are isolated from each other.
    Moreover, it has been proposed to extend the trench cross section in the lower region of the trench. The device to be insulated is arranged on the surface of the substrate (see DE 38 09 218 A1).
    The present invention relates to an integrated circuit device having at least two elements insulated from each other and a method of manufacturing the same.
    1 shows a substrate having a trench having a side with a bulge in the region under the trench.
    2 shows the substrate after the trench is filled with the first insulating layer.
    3 shows a substrate in which etching residues remain in the bulge after the first insulating layer is etched back.
    4 illustrates a substrate that involves the formation of insulating spacers.
    5 through 10 illustrate manufacturing steps of the memory cell device.
    5 shows a substrate involving first channel implantation.
    6 illustrates a substrate involving trench etching, second channel implantation, and formation of an insulating structure.
    7 shows a substrate involving the formation of word lines.
    FIG. 8 shows a cross-sectional view of the silicon substrate designated by VIII-VDP in FIG. 7.
    FIG. 9 shows a cross-sectional view of the silicon substrate designated by VIII-VIII in FIG. 7.
    FIG. 10 shows a top view of the silicon substrate shown in FIG. 7.
    The present invention relates to an integrated circuit device in which at least two elements are insulated from one another in a space saving manner and any damage to device characteristics due to the implantation required for isolation is avoided. The invention also relates to a method of manufacturing such an integrated circuit device.
    The problem is solved by an integrated circuit device according to claim 1 and a method according to claim 3 of the invention. Further refinements of the invention emerge from the dependent claims.
    The integrated circuit device according to the present invention is integrated in a semiconductor substrate. The semiconductor substrate preferably comprises a single crystalline silicon or single crystalline silicon layer of an SOI substrate.
    Arranged in the semiconductor substrate are trenches that reach from the main region of the semiconductor substrate to the semiconductor substrate. At least one side of the trench has an insulating structure that insulates the first device from the second device. The trench side with the insulating structure has a bulge as a result of the width of the trench being larger in the trench lower region than in the main region.
    The first element is arranged in the main region and the second element is arranged under the trench. The insulating structure covers the side arranged between the two elements. The increased thickness of the insulating structure in the bulge region ensures that parasitic MOS devices to be formed along the side will have a high threshold voltage at which no leakage current will occur at the surface of the side at operating voltage.
    The insulating structure reaches from the right side of the main region to the bottom of the trench. The thickness of the insulating structure, ie the range of the insulating structure perpendicular to the side, in this case is larger in the bulge area than in the main area. The lateral extent of the insulating structure according to the invention is larger in the substrate than in the main region of the substrate. As a result, the insulation effect of the insulation structure is improved when compared with the value that can be obtained with an insulation structure having a constant lateral range in the main region over the entire depth.
    Since the insulating structure is arranged on the side of the trench, the first element and the second element can be arranged directly in contact with each other when protruding on the main region. Since the first elements are arranged on the main region and the second elements are arranged under the trenches and an insulating structure is arranged on the trench sides between them, they are insulated from each other. The blocking action of the insulating structure can in this case be set in particular through the thickness of the insulating structure in the bulge region.
    The present invention can advantageously be used to construct a memory cell device. To this end, the integrated circuit device includes a plurality of identical strip shaped trenches that run substantially parallel. Each trench side has a bulge in the trench lower region and each has an insulating structure. A plurality of MOS transistors of the memory cell device, which are interconnected in series, are arranged in each case on the bottom of the trench and the main region between adjacent trenches. By using the self-aligned manufacturing method, it is possible to manufacture a memory cell device having a respective memory cell area requirement of 2F 2 . Where F is the minimum structure size in the individual technique.
    In order to produce the gray structure according to the invention, trenches having a larger width in the region under the trench than in the main region are manufactured in the main region of the substrate. The bulge on the trench side can be manufactured in several ways. On the other hand, the trench is manufactured by plasma etching, and the etching is performed in a parameter range in which a so-called barreling effect (also called bowing) occurs. This is understood to mean bulging in the lower region of the trench profile that occurs during the plasma etching of silicon when anisotropic etching increases to a pressure above that at which it is realized. For example, the barreling effect (or boeing) can be found in Engelhardt, S. Schwarzl, J. Electrochem. Soc., Vol. 134, p. 1985 (1987) and VLSI Electronic Microstructure Science, Vol. 8, Plasma Treatment for VLSI, NG Einspruch and DM Brown, Chapter 5 Academic Press Inc., Orlando, 1984, 124. This effect (also called boeing) can be observed when the RF power is reduced below the RF power at which anisotropic etching is realized. Other processes to produce barreling / boeing during silicon etching are HBr, O 2 , NF 3 with power less than 500W, power less than 50W.
    On the other hand, the trench profile can be realized by a combination of anisotropic and isotropic etching processes. Preferably, the anisotropic plasma etching process is performed in the first etching step and the isotropic plasma etching process or isotropic wet etching is performed in the second etching step. The isotropic plasma etch process may be performed in such a way that an etch byproduct, referred to as a sidewall passivation layer, is deposited on the sidewalls of the resulting trench. In etching trenches in silicon, the sidewall passivation layer comprises an oxide-like compound. The thickness of the sidewall passivation layer decreases toward the bottom of the trench. As a result, in the second isotropic etching step, the upper region of the trench side surface is protected against etchant attack and the bulge is formed only in the lower region of the trench.
    In order to form the insulating structure, the trench is preferably filled with a first insulating layer. The first insulating layer is selectively etched back to the substrate material by anisotropic etching. In the above treatment, the etching residue of the insulating material remains in the bulge of the trench. In essence the debris fills the bulge. The insulating spacer is formed on the side of the trench by the deposition of a second insulating layer having a conformal edge covering and the anisotropic etching back, and together with the etching residue arranged in the bulge, the insulating spacer in each case forms an insulating structure. do. In this way, the insulating structure is formed in such a way that it is self-aligned with the trench, ie without the use of a mask to be aligned with the trench. The trench can be formed with a minimum width of F (F: minimum structure width in individual techniques). The lateral extent of the insulating structure is determined by the depth of the bulge perpendicular to the side of the trench and the layer thickness of the second insulating layer on which the spacer is formed. The bulge is preferably formed with a radius of less than F / 4. Likewise the width of the spacer is preferably formed below F / 4. Therefore, the insulation voltage between the element on the main region and the element under the trench is increased by a factor of two compared to the value of the insulation voltage that can be formed when only the spacer is used as the insulating structure.
    The invention is now described in more detail using preferred embodiments and with reference to the accompanying drawings.
    The view in the figures is not the actual size.
    For example, the substrate 1 formed of single crystal silicon has a main region 2. For example, a trench mask formed of TEOS (not shown) is added to the main region 2. Using the trench mask as an etching mask, the trench 3 is etched into the substrate 1 (see FIG. 1). The trench 3 has, for example, a range of F perpendicular to the main region 2. The trench 3 has a bulge 3 'in the region below the trench. As a result, the width of the trench 3 is larger in the area under the trench than in the main area 2. In the main region 2, the trench 3 has a width of F. In contrast, the maximum width of the bulge 3 'region is F + 2 F / 4. F is the minimum structure size that can be produced by individual techniques. For example, F is 0.4 micrometer.
    The trench having a bulge (3 ') 3 are formed by plasma etching using HBr, O 2, NF 3 in the pressure range CBrF least three or at least 100 mTorr 15 mTorr pressure range. At this pressure, the bulge 3 'is formed by the barreling effect.
    Optionally, the trench 3 is an anisotropic plasma etch treatment with CBrF 3 at a pressure range of at least 100 mTorr and an HBr, O 2 , NF 3 or at least 15 mTorr and an isotropic plasma using NF 3 at a pressure range of at least 500 mTorr. It is formed by a combination of etching treatments. The bulge 3 'is formed during the isotropic etching process. A sidewall passivation layer deposited on the side of the trench 3 during the anisotropic plasma etch process protects the upper region of the trench 3 during the isotropic plasma etch.
    Further options for forming the trench 3 with the bulge 3 'are anisotropic plasma etching treatment with HBr, O 2 , NF 3 or CBrF 3 in a pressure range of at least 15 mTorr and aqueous It is composed by a combination of solutions or isotropic wet chemical etching with choline of KOH. In this case, the upper region of the trench side is protected against attack during isotropic etching by the sidewall passivation layer. The isotropic etching results in the formation of the bulge 3 '.
    For example, a first insulating layer 4 formed of SiO 2 is sequentially added to the main region 2. The first insulating layer 4 completely fills the trench 3. The first insulating layer 4 is deposited using the CVD method to at least F, i.e., a thickness of 0.4 mu m (see Fig. 2).
    After that, planarization is performed, in which the main region 2 of the substrate 1 is exposed. The planarization is performed by plasma assisted etching back or chemical mechanical polishing (CMP) of the first insulating layer.
    The remaining first insulating layer 4 is etched back during the selective anisotropic etching process with respect to silicon. In the treatment, the silicon surface is exposed on the trench bottom. The etching residue 4 'of SiO 2 remains in the bulge 3'. The etching back is performed using CHF 3 , CF 4 , Ar in a pressure range of 50 to 500 mTorr (see FIG. 3).
    For example, a second insulating layer formed of SiO 2 is deposited with essentially conformal edge covering. For example, the second insulating layer is deposited using a TEOS-CVD method with a thickness of 40 nm. The insulating spacer 5 is formed on the side of the trench 3 from the second insulating layer by anisotropic etching using CHF 3 , CF 4 , Ar in a pressure range of 50 to 500 mTorr. The spacer 5 has a width of approximately 40 nm. The lower portion of the trench is exposed between the spacers 5 on opposite sides of the trench 3 (see FIG. 4).
    A first device is fabricated in the main region 2 and a second device is fabricated below the trench. For example, the device is a MOS transistor. The first element is arranged from the side of the trench 3 which lies between the two elements and is insulated from the second element by an insulating structure consisting of individual insulating spacers 5 and etching residues 4 '. If a conductive layer is arranged on the surface of the spacer 5, a parasitic MOS element is formed between the two elements, which element is at least 15 volts, ie MOS, because of the thickness of the insulating structure in the region of the bulge 3 ′. Has a threshold voltage above the standard operating voltage for the transistor.
    Fabrication of read-only memory cell devices with improved vertical insulators is described below with reference to FIGS. The memory cells of the read only memory cell device take the form of MOS transistors and have different threshold voltages depending on the information stored in the individual memory cells.
    In order to fabricate the read-only memory cell device in a substrate 11 made of, for example, single crystal silicon, an insulating structure defining an area for the read-only memory cell device is first given a main area 12 of the substrate 11. (Not shown). For example, the substrate 11 is p-doped at a dopant concentration of 10 16 cm −3 .
    The area for the depletion channel of the MOS transistor is then defined with the aid of the photolithographic method. The depletion channel 13 is formed with the aid of first channel implantation using arsenic with an energy of 50 KeV and a dose of 4 × 10 12 cm −2 (see FIG. 5). When using the 0.4 μm technique, the range of the depletion channel 13 is, for example, 0.6 μm × 0.6 μm.
    After the SiO 2 layer is deposited to a thickness of 200 nm with the aid of the TEOS method, a trench mask is formed by structuring the SiO 2 layer with the aid of the photolithographic method (not shown). Using the trench mask as an etching mask, the longitudinal trench 14 is etched by anisotropic etching with Cl 2 . The longitudinal trench 14 has a depth of 0.6 μm, for example. The width of the depletion channel 13 is set during the etching of the longitudinal trench 14. Therefore, the alignment of the trench mask with respect to the depletion channel 13 is not critical.
    In the case of a 0.4 μm technique, the width of the longitudinal trench 14 is 0.4 μm and the spacing between adjacent longitudinal trenches 14 is likewise 0.4 μm. The length of the longitudinal trench 14 depends on the size of the memory cell device and is for example 130 μm.
    The side of the longitudinal trench 14 has a bulge 14 ′ in the lower region of the longitudinal trench 14. Such bulges are formed, for example, by isotropic etching with choline in an aqueous solution. The bulge 14 ′ has a maximum depth of 100 nm perpendicular to the side of the longitudinal trench 14.
    The longitudinal trench 14 with the bulge 14 ′ is filled by CVD deposition of the first insulating layer. The main region 2 is subsequently exposed again by planarization by selective anisotropic plasma etching or chemical mechanical polishing (CMP). The first insulating layer is etched back by anisotropic etching selectively to silicon using CHF 3 , CF 4 , Ar. In the process, the lower part of the longitudinal trench 14 is exposed. The etching residue 15 formed of SiO 2 and filling the bulge 14 ′ remains in the region of the bulge 14 ′.
    Next, the region for the depletion channel for MOS transistors which are sequentially formed under the longitudinal trench 14 is defined with the aid of the photolithographic method. The depletion channel 16 is formed in the lower portion of the longitudinal trench 14 by, for example, a second channel implantation using arsenic with an energy of 50 KeV and a dose of 4 × 10 12 cm −2 (see FIG. 6). ). The area between adjacent longitudinal trenches 6 is here masked by a trench mask. Therefore, the alignment during the definition of the depletion channel 16 is not critical. The second channel implant is self aligned with respect to the sidewall of the longitudinal trench 14.
    The trench mask is sequentially wet chemically removed using, for example, NH 4 F / HF. Spacers 17 formed of SiO 2 are formed on the sidewalls of the longitudinal trench 14 by deposition of additional SiO 2 layers using the TEOS method and sequential anisotropic etching. The anisotropic etching is performed using CHF 3 , CF 4 , Ar. The spacer 17 and the etching residue 15 together form the insulating structure that insulates adjacent MOS transistors.
    After the sacrificial oxide is grown and etched, the gate oxide layer 18 is grown to a thickness of 10 nm. The gate oxide layer 18 is arranged between the lower portion of the longitudinal trench 14 and the longitudinal trench 14 on the main region 12 (FIG. 7, designated by FIGS. See Fig. 8 showing the section passing through Fig. 9 and Fig. 9 showing the section passing through Fig. 7 designated by VIII-VIII. The section shown in Fig. 7 is the VIII-VIII in Figs. Is specified by
    A polysilicon layer is deposited over the entire area up to a thickness of 400 nm. By structuring the polysilicon layer in the photolithographic processing step, word lines 19 are formed to travel along the main region 12 perpendicular to the longitudinal trench 14. In each case the width and spacing between the word lines 19 correspond to a minimum structure size F of F = 0.4 μm, for example. The word line 19 proceeds in such a way that the depletion channel 16 formed below the longitudinal trench 14 is individually arranged below the word line 19.
    Source / drain implantation is performed sequentially using, for example, arsenic with an energy of 25 KeV and a dose of 5 × 10 15 cm −2 . During the source / drain implantation, doped regions 20 are formed in the main region 12 between the longitudinal trenches 14 below the longitudinal trenches 14. The doped region 20 functions as a common source / drain region for two adjacent MOS transistors each arranged along a row. The word line 19 is doped simultaneously during the source / drain implantation.
    The side of the word line 19 is covered with a spacer 21 by deposition of an additional SiO 2 layer and anisotropic etching back. The source / drain implantation is performed in a self aligned manner with respect to the word line 19. Since the doped region 20 is doped by the same conductivity type as the depletion channels 13, 16, the alignment during the depletion channel definition being in a direction parallel to the course of the longitudinal trench 14 is It doesn't matter. Of the doped region 20 parallel to the main region 12, corresponding to the distance between adjacent word lines 19, the distance between adjacent longitudinal trenches 14 and the dimensions of the longitudinal trenches 14. The area is at most F × F. In other words, it is 0.4 micrometer x 0.4 micrometer, for example.
    Two adjacent doped regions 20 and in each case said word line 19 arranged between them form a MOS transistor. Rows of MOS transistors formed from two doped regions 20 interconnected in series and with word lines 19 arranged therebetween are in each case the bottom of the longitudinal trench 14 and the longitudinal direction. It is arranged between the trenches 14. The MOS transistors arranged under the longitudinal trenches 14 are insulated from adjacent MOS transistors arranged between the longitudinal trenches 14 by an insulating structure consisting of spacers 17 and etching residues 15. The insulating structure has a maximum thickness of approximately 150 nm, with the result that the threshold voltage of the parasitic MOS transistor formed on the side of the longitudinal trench 14 is high enough to prevent leakage current.
    At the edge of the read-only memory cell device, each row has two connections, with the MOS transistors arranged in rows between them in series (not shown). The MOS transistors arranged in individual rows can be driven with the sense of a NAND architecture through the connections.
    Considering that each doped region 20 is a source / drain for two adjacent MOS transistors, each MOS transistor length parallel to the course of the longitudinal trench 14 is 2F. The width of the MOS transistor is F in each case. Therefore, the area for the memory cell formed from the MOS transistor is 2F 2 defined by the fabrication. Memory cells that are contiguous along the word line 19 and have contours Z1 and Z2 shown as gothic lines in the plan view of FIG. 10 are directly adjacent to each other when projected relative to the main area 12. The memory cell Z1 is arranged under the longitudinal trench 14, while the memory cell Z2 is arranged on the main region 12 between two adjacent longitudinal trenches 14. By arranging adjacent memory cells in two vertical offset planes, the packing density is increased without damaging the insulation between adjacent memory cells.
    The read only memory cell device is programmed during a first channel injection and a second channel injection. The depletion channels 13 and 16 are formed only for the MOS transistors to which the first logic value is assigned. The second logic value is assigned to another MOS transistor.
    The read-only memory cell device is completed by deposition contact hole etching of intermediate oxides and addition and structure of the metal layer. Such known processing steps are not described.
    Although the present invention has been described above in accordance with one preferred embodiment of the present invention, various modifications may be made without departing from the spirit of the present invention as defined by the appended claims. It is obvious to those skilled in the art.
    权利要求:
    Claims (7)
    [1" claim-type="Currently amended] The first and second elements are integrated in the semiconductor substrate 1,
    A trench 3 is arranged in the semiconductor substrate 1, the trench 3 reaching from the main region 2 of the semiconductor substrate 1 to the semiconductor substrate 1 and the first element and the With insulating structures 4 ', 5 for insulating the second element,
    At least one side of the trench 3 has a bulge 3 'such that the width of the trench 3 is larger in the region below the trench than in the region of the main region 2,
    The insulating structures 4 ', 5 are adjacent to the sides of the trench and reach from the main region 2 to the lower part of the trench in a direction perpendicular to the main region 2, the insulating structures 4', The thickness of 5) is greater in the area of the bulge 3 'than in the main area 2,
    The first element is arranged on the main region (2), the second element being arranged under the trench.
    [2" claim-type="Currently amended] The method of claim 1,
    A plurality of identical strip-shaped trenches 14 are provided in the region below the trench, with sides with bulges 14 'and sides with insulating structures 14' and 17, respectively, running in parallel,
    A plurality of MOS transistors of the memory cell device interconnected in series are arranged in each case on the main region (12) and under the trench between adjacent trenches (14).
    [3" claim-type="Currently amended] An integrated circuit device manufacturing method having at least two mutually insulated elements, the method comprising:
    A trench 3 is formed in the main region 2 of the semiconductor substrate 1, wherein the trench has a bulge 3 ′ on at least one side of the lower portion of the trench, the trench width being the main Larger in the bulge than in the area 2,
    An insulating structure (4 ', 5) is formed on the side with the bulge (3'), the insulating structure extending from the main area (2) to the bottom of the trench, in the main area Thicker in the area of the bulge 3 ',
    -Forming a first element and a second element in such a way that they are insulated from each other by said insulating structures 4 ', 5,
    The first device is formed on the main region (2) of the semiconductor substrate, and the second device is formed under the trench.
    [4" claim-type="Currently amended] The method of claim 3,
    An etching process is performed by a two-step etching to form the trench (3), wherein the anisotropic etching is performed by the first etching step, and the isotropic etching is performed by the second etching step.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    An anisotropic plasma etching process is performed in the first etching step, and an isotropic plasma etching process or an isotropic wet etching process is performed in the second etching process.
    [6" claim-type="Currently amended] The method according to claim 3 to 5,
    The trench 3 is formed as a longitudinal trench,
    The trench 3 is filled with a first insulating layer 4 to form the insulating structures 4 ', 5,
    The first insulating layer 4 is etched back by anisotropic etching selectively to the semiconductor substrate 1, and the etching residue 4 'remains to fill the bulge 3',
    An insulating spacer (5) is formed on at least one side of the trench (3) by deposition and anisotropic etching back of the second insulating layer having a conformal edge covering, said insulating spacer (4 ') and And forming the insulating structure together.
    [7" claim-type="Currently amended] The method of claim 6,
    A plurality of longitudinal trenches 14 are formed, the trenches running in parallel, having sides with bulges 14 'in the region below the trenches and sides with insulating structures 15 and 17, respectively; ,
    Fabricating an integrated circuit device, characterized in that a plurality of MOS transistors of a series of interconnected memory cell devices are formed in each case on the main region 12 and under the trench between adjacent longitudinal trenches 14. Way.
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    同族专利:
    公开号 | 公开日
    JPH11509043A|1999-08-03|
    EP0838089B1|2001-09-19|
    KR100418849B1|2004-04-21|
    CN1093983C|2002-11-06|
    WO1997003463A1|1997-01-30|
    DE19525072A1|1997-01-16|
    IN189112B|2002-12-21|
    CN1190490A|1998-08-12|
    EP0838089A1|1998-04-29|
    DE19525072C2|2002-06-27|
    AR002791A1|1998-04-29|
    US5990536A|1999-11-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1995-07-10|Priority to DE19525072.9
    1995-07-10|Priority to DE1995125072
    1996-06-24|Application filed by 로더리히네테부쉬, 지멘스악티엔게젤샤프트
    1999-02-25|Publication of KR19990014889A
    2004-04-21|Application granted
    2004-04-21|Publication of KR100418849B1
    优先权:
    申请号 | 申请日 | 专利标题
    DE19525072.9|1995-07-10|
    DE1995125072|DE19525072C2|1995-07-10|1995-07-10|Integrated circuit arrangement in which a first component is arranged on a main surface of a semiconductor substrate and a second component on the trench bottom, and method for the production thereof|
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